KTH EECS

Networks-on-Chip (NoC) has emerged as a solution to address the communication demands of many-core architectures; and it is composed of links and routers. Designing deadlock-free and fault-tolerant routing algorithms in NoCs is one of the most important issues in achieving a higher performance and better reliability. In this talk, a visualization framework for routing and mapping algorithms will be introduced. Then a systematic way to design deadlockfree routing algorithms will be presented. Finally, a reconfigurable router architecture will be suggested that allows testing multiple routers at high speed.