WCET 2019 – Call for Papers

Call for Papers

19th International Workshop on Worst-Case Execution Time Analysis

(WCET 2019)

Stuttgart, Germany

July 9, 2019

www.ecrts.org/wcet

The 19th International Workshop on Worst-Case Execution Time Analysis (WCET  2019) focuses on the analysis and design of real-time systems in a broad sense, with a particular emphasis on techniques to analyze the worst-case execution time (WCET) of real-time software. The workshop covers topics related to hard and soft real-time systems, program analysis, timing analysis, the integration of WCET and schedulability analysis as well as (timing-predictable) hardware designs and operating systems. As in previous years, the 19th edition of the WCET workshop will be co-located with the Euromicro Conference on  Real-Time Systems (ECRTS 2019) in Stuttgart, Germany, from July 9-12, 2019.

IMPORTANT DATES

Paper submission deadline:           April 16, 2019 (23:59 GMT-12)

Notification of acceptance:          May 14, 2019

Early registration deadline:         May 29, 2019

Camera-ready version deadline:       May 29, 2019

Workshop:                            July 9, 2019

GOALS AND TOPICS

A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy timing requirements, often under resource constraints. The analysis of such real-time systems is often challenging due to the interaction of the physical environment with the system’s software, which in turn interacts with the underlying hardware as well as other software components. All these interactions make it difficult in practice to guarantee that a system meets all its timing requirements. Designers and engineers thus strive for their systems to be timing-predictable and analyzable, i.e., facilitate the verification of the system’s timing behavior.

The WCET workshop covers all aspects related to timing analysis and the design of timing-predictable systems, with a particular emphasis on worst-case execution time (WCET) analysis. Topics of interest include, but are not limited to:

  • Integration of WCET and schedulability analysis
  • Processor and hardware design for timing predictability
  • WCET analysis of multi-threaded and parallel applications
  • WCET analysis for multi/many-core systems and GPUs
  • Integration of WCET analysis in development processes
  • Timing-predictable, resource-aware operating systems
  • Program design for timing predictability
  • Flow analysis for WCET, loop bounds, infeasible paths
  • Low-level timing analysis, modeling/analysis of processor features
  • Measurement-based and hybrid WCET analysis
  • Tools for WCET analysis
  • Compiler-based optimization of worst-case timing
  • Methods and benchmarks for WCET analysis evaluation
  • Case studies and industrial experiences of WCET analysis
  • WCET analysis in the academic curriculum

Statements which are innovative, controversial, or that present new approaches are especially sought.

SUBMISSION INSTRUCTIONS

Research papers should present original research results not published or submitted for publication in other forums. Accepted papers will be published via Schloss Dagstuhl’s OASIcs online proceedings series. By submitting a paper, the authors agree and confirm that: (1) Neither this paper, nor a version close to it, is under submission or will be submitted elsewhere before notification by WCET 2019. (2) If accepted, at least one author will register for WCET 2019, and present the paper at the workshop in person.

Papers submitted for the WCET workshop must be written in English, must not exceed 10 pages, excluding bibliography, should conform with the OASIcs typesetting requirements, and must be submitted in PDF format using the WCET workshop paper submission website. The bibliography does not count towards the page limit of 10 pages. Author names, affiliations and self-references should not be anonymized.

See http://www.dagstuhl.de/publikationen/oasics/anleitung-fuer-autoren/

PROGRAM CHAIR

Sebastian Altmeyer, University of Amsterdam, The Netherlands

PROGRAM COMMITTEE

  • Clement Ballabriga, Lille 1 University, France
  • Florian Brandner, Télécom ParisTech, Université Paris-Saclay, France
  • Adam Betts, Rapita Systems, UK
  • Heiko Falk, TU Hamburg, Germany
  • Björn Lisper, Mälardalen University, Sweden
  • Claire Maiza, Grenoble INP/Verimag, France
  • Enrico Mezzetti, Barcelona Supercomputing Center, Spain
  • Kartik Nagar, Purdue University, United States
  • Isabelle Puaut, University of Rennes I/IRISA, France
  • Jan Reineke, Saarland University, Germany
  • Christine Rochange, IRIT, France
  • Abhik Roychoudhury, National University of Singapore, Singapure
  • Martin Schoeberl, Technical University of Denmark, Denmark
  • Peter Wägemann, FA Universität Erlangen-Nürnberg, Germany
  • Simon Wegener, AbsInt Angewandte Informatik GmbH, Germany
  • Jakob Zwirchmayr, TTTech Computertechnik AG – Automotive, Austria

STEERING COMMITTEE 

  • Björn Lisper, Mälardalen University, Sweden
  • Isabelle Puaut, University of Rennes I/IRISA, France
  • Jan Reineke, Saarland University, Germany
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