IEEE Transactions on Nanotechnology



The IEEE Transactions on Nanotechnology (TNANO) publishes novel and important results in engineering at the nanoscale.  


TNANO 2016 Impact Factor

IEEE Transactions on Nanotechnology (TNANO) is pleased to announce a new 2016 impact factor (IF) of 2.485*! This represents 46% increase from the 2015 IF, upholding the TNANO’s status as one of the leading peer-reviewed journals in the field of nanotechnology. The official journal of IEEE Nanotechnology Council (NTC), TNANO publishes a collection of peer-reviewed articles and short reports (i.e., letters) of original research and perspectives and reviews and mini-reviews on emerging topics. TNANO offers rapid peer-review and can publish an accepted article online through IEEE Xplore as soon as it is submitted in final form. Web-published papers have DOI (Digital Object Identifier), and are fully citable and downloadable. Make sure your manuscript has the impact and gets the attention it deserves by submitting your article to TNANO today.

*2016 Journal Citation Reports published by Clarivate Analytics, 2017

Article in Focus from the May 2017 issue of IEEE Transactions on Nanotechnology


Crossbar-Based Memristive Logic-in-Memory Architecture

by Georgios Papandroulidakis ; Ioannis Vourkas ; Angel Abusleme ; Georgios Ch. Sirakoulis ; Antonio Rubio
T-NANO, Vol. 16, Issue 3, pp. 491 – 501, May 2017.

Abstract: The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.


Announcement: ENANO becomes “Letters” in TNANO

The IEEE Nanotechnology Council (NTC) is excited to announce the launch of the category “Letters” in IEEE Transactions on Nanotechnology (TNANO) by merging IEEE Nanotechnology Express (ENANO) with TNANO. Led by the newly appointed Associate Editor-in-Chief, Prof. Gwo-Bin Lee, under the leadership of the Editor-in-Chief, Prof. Fabrizio Lombardi, the “Letters” in TNANO serves as forum for rapid publication of high-quality articles – featuring the topics of great current interest in all areas of nanotechnology, including nanoscale materials, devices, systems, and applications, and their underlying science, which cover the interdisciplinary and multidisciplinary areas across engineering, material science, physics, chemistry, biology, medicine, and related disciplines.

The “Letters” in TNANO publishes a collection of peer-reviewed short reports of original research and perspectives and mini-reviews on emerging topics. Papers submitted to the “Letters” are limited to a maximum of 4 journal pages in the two-column IEEE format, which includes figures, tables, and references. The “Letters” in TNANO maintains the same competitive and constructive peer-review criteria of TNANO with no article publishing charges.

TNANO is now accepting submissions for the “Letters”. The TNANO manuscript submission process is fully electronic to ensure the rapid publication of results. Manuscripts should be submitted via ScholarOne Manuscripts at . The submission to publication time is expected to be approximately six weeks. Accepted papers are published on the web in IEEE Xplore as soon as they are submitted in final form. Web-published papers have a DOI (Digital Object Identifier), and are fully citable and downloadable.

Submit your manuscript to the “Letters” in TNANO!

Information about TNANO

TNANO focuses on nanoscale devices, systems, materials and applications, and on their underlying science. It is an interdisciplinary journal that covers all areas of nanotechnology. The hardcopy version is published bi-monthly, but accepted papers are published on the web as soon as they are submitted in final form. TNANO is a publication of the IEEE Nanotechnology Council.

TNANO is a Hybrid Journal, which means that it allows either:

  • Traditional manuscript submission
  • Open Access (author-pays OA) manuscript submission at a discounted rate

 TNANO publishes Research Letters, Regular Papers, and Correspondence Items. Research Letters must not exceed three printed pages. They are subject to the same thorough review process as Regular Papers, but receive priority treatment. A Research Letter that is accepted without major revisions is expected to be published on the web within 4 to 6 weeks of its initial submission.

Areas covered by TNANO include, but are not limited to:

  • Nano and Molecular Electronics
  • Circuits and Architectures
  • Nanomagnetism and Spintronics
  • Nano-Optics, Nano-Optoelectronics and Nanophotonics
  • Nanorobotics and Nanoassembly
  • Nanosensors and Nanoactuators
  • Nanomechanics and Nanoelectromechanical Systems
  • Nanobiotechnology and Nanomedicine
  • Nanofabrication and Nanolithography
  • Nanometrology and Characterization
  • Computational Nanotechnology

Additional information on these is found here.