IEEE Transactions on Nanotechnology



The IEEE Transactions on Nanotechnology (TNANO) publishes novel and important results in engineering at the nanoscale.  


Message from the Editor-In-Chief

Also this year as the flagship publication of the IEEE Nanotechnology Council (NTC), I am pleased to report that the IEEE Transactions on Nanotechnology (TNANO) has achieved new heights across all endeavors of operation.

2017 is the third consecutive year with record numbers in terms of number of submissions; moreover, selectivity has remained nearly constant, so confirming that TNANO has reached an excellent level of overall scholarship. In quantitative terms, Manuscript Central Scholar One reports the following very impressive statistics for the 2017 calendar year (the data for 2016 is reported between parentheses):

  • Number of regular manuscript submissions: 797 (758)
  • Number of “Letter” submissions: 124 (0)
  • Total number of submissions: 921 (758)
  • Acceptance rate: 31% (28%)
  • Rejection rate: 50% (54%)
  • Revise-and-resubmit rate: 19% (18%)

Read the rest of the editorial here.

Special Issue on Current Trends in Nanoelectronic Circuits and System Design

IEEE Transactions on Nanotechnology (TNANO) Special Section/Issue on Current Trends in Nanoelectronic Circuits and System Design

To enable next generation sensing, control, and computing, in reality, advanced nanoelectronic devices and circuits must be developed and co-optimized across multiple hierarchical levels in order to sense, process and transmit data, while satisfying the demanding performance requirements for high speed, low power, flexible reconfigurability, high reliability etc. In addition, with the increasing complexity and data volume of sensing and computing, novel designs must be explored to improve design efficiency, enhance reliability and reduce time-to-market. For these reasons, there is an immediate need to re-think the conventional design strategies for implementing the next-generation sensing, control, and computing paradigm. This special issue focuses on novel device technology and circuit designs to implement smart, efficient, reliable and secure sensing, control, and computing paradigm. The topics of interest include:

  • Nanoelectronic devices with ultra-high energy efficiency
  • Energy-efficient analog front end and wireless communication circuits using nanoelectronic devices
  • Emerging device and memory technology for information processing and storage
  • Emerging device, including but not limited to GFET, TFET, Graphene nanoribbon tunnel FET, for digital, analog, and RF circuit design
  • Emerging memory, including but not limited to phase change memory, magnetic device, resistive memory, for digital, analog, and RF circuit design
  • Nano-sensors for data sensing in Internet of Things
  • Nano-CMOS and Post-CMOS based circuits for big data processing
  • Nanoelectronic technology based sensors and controller for Cyber-Physical Systems
  • Security and reliability solutions for nanoelectronic devices and circuits
  • Nanoelectronic devices and circuits for secure sensing
  • Novel devices and circuits for non-conventional computing
  • Neuromorphic circuits and architectures
  • Nano-CMOS and Post-CMOS based sensors and circuits for smart grid
  • Case studies for sensors and circuits designed using nanoelectronic technology

Submission Information:

All manuscripts must be submitted online using the IEEE TNANO manuscript template and Information for
Authors, via the IEEE Manuscript Central found at On submission, authors must select the “Special Issue” manuscript type instead of “Regular Paper.” Authors are suggested to clearly mention in the cover letter to the Editor-in- Chief (EiC) during the submission that the manuscript is for this specific Special Issue. Manuscripts must focus on nanotechnology as reflected by technical content and references.

Important Dates

  • Submission Deadline: 15 January 2018
  • Author Notification: 15 March 2018 (Tentative)
  • Revised Manuscript Due: 15 April 2018 (Tentative)
  • Notification of Acceptance: 15 May 2018 (Tentative)

Guest Editors

Please address all other correspondence regarding this Special Issue to the Guest Editors using the following email-ID:

  • Michael Huebner, Ruhr University of Bochum, Michael.Huebner@ruhr-uni-
  • Mircea Stan, University of Virginia,
  • Nikolaos Voros, Technological Educational Institute of Western Greece,

Article in Focus from the May 2017 issue of IEEE Transactions on Nanotechnology


Crossbar-Based Memristive Logic-in-Memory Architecture

by Georgios Papandroulidakis ; Ioannis Vourkas ; Angel Abusleme ; Georgios Ch. Sirakoulis ; Antonio Rubio
T-NANO, Vol. 16, Issue 3, pp. 491 – 501, May 2017.

Abstract: The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.


Announcement: ENANO becomes “Letters” in TNANO

The IEEE Nanotechnology Council (NTC) is excited to announce the launch of the category “Letters” in IEEE Transactions on Nanotechnology (TNANO) by merging IEEE Nanotechnology Express (ENANO) with TNANO. Led by the newly appointed Associate Editor-in-Chief, Prof. Gwo-Bin Lee, under the leadership of the Editor-in-Chief, Prof. Fabrizio Lombardi, the “Letters” in TNANO serves as forum for rapid publication of high-quality articles – featuring the topics of great current interest in all areas of nanotechnology, including nanoscale materials, devices, systems, and applications, and their underlying science, which cover the interdisciplinary and multidisciplinary areas across engineering, material science, physics, chemistry, biology, medicine, and related disciplines.

The “Letters” in TNANO publishes a collection of peer-reviewed short reports of original research and perspectives and mini-reviews on emerging topics. Papers submitted to the “Letters” are limited to a maximum of 4 journal pages in the two-column IEEE format, which includes figures, tables, and references. The “Letters” in TNANO maintains the same competitive and constructive peer-review criteria of TNANO with no article publishing charges.

TNANO is now accepting submissions for the “Letters”. The TNANO manuscript submission process is fully electronic to ensure the rapid publication of results. Manuscripts should be submitted via ScholarOne Manuscripts at . The submission to publication time is expected to be approximately six weeks. Accepted papers are published on the web in IEEE Xplore as soon as they are submitted in final form. Web-published papers have a DOI (Digital Object Identifier), and are fully citable and downloadable.

Submit your manuscript to the “Letters” in TNANO!

Information about TNANO

TNANO focuses on nanoscale devices, systems, materials and applications, and on their underlying science. It is an interdisciplinary journal that covers all areas of nanotechnology. The hardcopy version is published bi-monthly, but accepted papers are published on the web as soon as they are submitted in final form. TNANO is a publication of the IEEE Nanotechnology Council.

TNANO is a Hybrid Journal, which means that it allows either:

  • Traditional manuscript submission
  • Open Access (author-pays OA) manuscript submission at a discounted rate

 TNANO publishes Research Letters, Regular Papers, and Correspondence Items. Research Letters must not exceed four printed pages. They are subject to the same thorough review process as Regular Papers, but receive priority treatment. A Research Letter that is accepted without major revisions is expected to be published on the web within 4 to 6 weeks of its initial submission.

Areas covered by TNANO include, but are not limited to:

  • Nano and Molecular Electronics
  • Circuits and Architectures
  • Nanomagnetism and Spintronics
  • Nano-Optics, Nano-Optoelectronics and Nanophotonics
  • Nanorobotics and Nanoassembly
  • Nanosensors and Nanoactuators
  • Nanomechanics and Nanoelectromechanical Systems
  • Nanobiotechnology and Nanomedicine
  • Nanofabrication and Nanolithography
  • Nanometrology and Characterization
  • Computational Nanotechnology

Additional information on these is found here.