IEEE Transactions on Nanotechnology
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The IEEE Transactions on Nanotechnology (TNANO) publishes novel and important results in engineering at the nanoscale.  


Article in focus: August 2016

From the September 2016 issue of IEEE Transactions on Nanotechnology

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

by YYasunao Katayama; Toshiyuki Yamane; Daiju Nakano; Ryosho Nakane; Gouhei Tanaka
T-NANO, Vol. 15, Issue 5, pp. 762 – 769, September 2016.

 
Immagine

Abstract: We present a framework of wave-based neuromorphic computing aiming at brain-like capabilities and efficiencies with nanoscale device integration. We take advantage of the unique nature of elastic nondissipative wave dynamics in both computations and IO communications in between as a means to natively implement and execute neuromorphic computing functions such as weighted sum in a spatiotemporal manner. Lower bound analysis based on a memory model and wave group velocity scaling is provided for conceptual evaluations.
 


 

Article in focus: August 2016

From the July 2016 issue of IEEE Transactions on Nanotechnology

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

by Kamela C. Rahman; Dan Hammerstrom; Yiwei Li; Hongyan Castagnaro; Marek A. Perkowski
T-NANO, Vol. 15, Issue 4, pp. 675 – 686, July 2016.

teaser0816

Abstract: Continued dimensional scaling of CMOS processes is approaching fundamental limits and, therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks. This paper involves the design of a memristor-based massively parallel datapath for various applications, specifically single instruction multiple data and parallel pipelines. The innovation of our approach is that the datapath design is based on space-time diagrams that use stateful IMPLY gates built from binary memristors. The paper also develops a new model and methodology to design massively parallel memristor-CMOS hybrid datapath architectures at a system level. This methodology is based on an innovative concept of two interacting subsystems: 1) a controller composed of a memristive RAM, MsRAM, to act as a pulse generator, along with a finite-state machine realized in CMOS, a CMOS counter, CMOS multiplexers, and CMOS decoders; 2) massively parallel pipelined datapath realized with a new variant of a CMOL-like nanowire crossbar array, memristive stateful CMOL with binary stateful memristor-based IMPLY gates. In contrast to previous memristor-based FPGA, our proposed memristive stateful logic field programmable gate array uses memristors for both memory and combinational logic implementation. With a regular structure of square abutting blocks of memristive nanowire crossbars and their short connections, our architecture is highly reconfigurable. We present the design of a pipelined Euclidean distance processor along with its various applications. Euclidean distance calculation is widely used by many neural network and similar algorithms.

 


 

Call for papers

The call for papers for two special issues has been launched. More information are available here.
 


Message from the Editor-In-Chief

by Fabrizio Lombardi

 

On December 31 2015, I completed the first year of my term as Editor-In-Chief (EIC); as you will read further in this editorial, I am pleased to report that the IEEE Transactions on Nanotechnology (TNANO) continues to strengthen its reputation and consolidate its role as the flagship Transactions of the IEEE Nanotechnology Council (NTC). 2015 has been an outstanding year for TNANO; Manuscript Central Scholar 1 reports the following very impressive statistics for the 2015 calendar year:

Number of submitted original papers: 647
Number of revised-and-resubmitted papers: 99
Total number of papers received: 746
Acceptance rate: 30.4%
Rejection rate: 51.6%
Revise-and-resubmit rate: 18%

All the above numbers are the absolute best in quantitative and qualitative terms (such as for the highest selectivity) in the 14 years of existence of TNANO and reflect the steady and continued growth in terms of quality and quantity of this periodical. (continue to read)


Information about TNANO

TNANO focuses on nanoscale devices, systems, materials and applications, and on their underlying science. It is an interdisciplinary journal that covers all areas of nanotechnology. The hardcopy version is published bi-monthly, but accepted papers are published on the web as soon as they are submitted in final form. TNANO is a publication of the IEEE Nanotechnology Council.

TNANO is a Hybrid Journal, which means that it allows either:

  • Traditional manuscript submission
  • Open Access (author-pays OA) manuscript submission at a discounted rate


 TNANO publishes Research Letters, Regular Papers, and Correspondence Items. Research Letters must not exceed three printed pages. They are subject to the same thorough review process as Regular Papers, but receive priority treatment. A Research Letter that is accepted without major revisions is expected to be published on the web within 4 to 6 weeks of its initial submission.


Areas covered by TNANO include, but are not limited to:

  • Nano and Molecular Electronics
  • Circuits and Architectures
  • Nanomagnetism and Spintronics
  • Nano-Optics, Nano-Optoelectronics and Nanophotonics
  • Nanorobotics and Nanoassembly
  • Nanosensors and Nanoactuators
  • Nanomechanics and Nanoelectromechanical Systems
  • Nanobiotechnology and Nanomedicine
  • Nanofabrication and Nanolithography
  • Nanometrology and Characterization
  • Computational Nanotechnology


Additional information on these is found here.