IEEE Transactions on Nanotechnology
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Archive for December, 2015

2016 TNANO Best Paper Award

Thursday, December 17th, 2015

At the beginning of each year, T-NANO selects a paper that appeared in the Transactions during the previous calendar year for its Best Paper Award.  Candidate papers are nominated by members of the Editorial Board.  Evaluation is done by members of the Senior Editors Panel, with criteria including technical merit, originality, potential impact on the field, clarity of presentation, and practical significance for applications.  The award includes a certificate for each of the co-authors, and a check of $1000 to be divided among the co-authors.  The award is presented at the Award Ceremony at the annual IEEE International Conference on Nanotechnology.

This yearly award will be made starting in 2017 for the best paper published in TNANO in 2016.

Detailed information about the Best Paper Award are available here.

 

 

 

Special Issue on Nanoelectronic Devices and Circuits

Friday, December 4th, 2015

Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing

IEEE Transaction on Nanotechnology (TNANO) seeks original research manuscripts for a Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.

The next generation paradigm of information processing may involve a network of interconnected physical objects such as computers, mobile phones, sensors, actuators, wearable devices, vehicles, homes, buildings, and even energy systems, in which continuous sensing and computing takes place. In such a computing paradigm the vision is to connect a large amount of objects, allow them to collect and exchange data through network connectivity, and consequently utilize the enormous data for analytics and operation. Such as infrastructure provides increasingly smart, reliable and secure services among different things for different users. It has been extensively applied to diverse application domains, such as environmental monitoring, security surveillance, smart power grids, energy-efficient buildings, and interconnected vehicles.

To enable next generation sensing, control, and computing, in reality, advanced nanoelectronic devices and circuits must be developed and co-optimized across multiple hierarchical levels in order to sense, process and transmit data, while satisfying the demanding performance requirements for high speed, low power, flexible reconfigurability, high reliability etc. In addition, with the increasing complexity and data volume of sensing and computing, novel designs must be explored to improve design efficiency, enhance reliability and reduce time-to-market. For these reasons, there is an immediate need to re-think the conventional design strategies for implementing the next-generation sensing, control, and computing paradigm.

This special issue focuses on novel device technology and circuit designs to implement smart, efficient, reliable and secure sensing, control, and computing paradigm. The topics of interest include, but are not limited to the following:

  • Nanoelectronic devices with ultra-high energy efficiency
  • Energy-efficient analog front end and wireless communication circuits using nanoelectronic devices
  • Emerging device and memory technology for information processing and storage
  • Emerging device, including but not limited to GFET, TFET, Graphene nanoribbon tunnel FET, fordigital, analog, and RF circuit design
  • Emerging memory, including but not limited to phase change memory, magnetic device, resistive memory, for digital, analog, and RF circuit design
  • Nano-sensors for data sensing in Internet of Things
  • Nano-CMOS and Post-CMOS based circuits for big data processing
  • Nanoelectronic technology based sensors and controller for Cyber-Physical Systems
  • Security and reliability solutions for nanoelectronic devices and circuits
  • Nanoelectronic devices and circuits for secure sensing
  • Novel devices and circuits for non-conventional computing
  • Neuromorphic circuits and architectures
  • Nano-CMOS and Post-CMOS based sensors and circuits for smart grid
  • Case studies for sensors and circuits designed using nanoelectronic technology

Submission Information:

All manuscripts must be submitted online using the IEEE TNANO manuscript template and Information for Authors, via the IEEE Manuscript Central found at https://mc.manuscriptcentral.com/tnano. On submission, authors must select the “Special Issue” manuscript type instead of “Regular Paper.” Manuscripts must focus on nanotechnology as reflected by technical content and references.

Special Issue Timeline:

The following is the tentative timeline for the special issue:

  • Submission Deadline: 1 October 2016
  • Author Notification: 1 December 2016
  • Revised Manuscript Due: 15 January 2017
  • Notification of Acceptance: 15 February 2017
  • Final Manuscript Due: 15 April 2017
  • Tentative Publication Date: Late 2017

Guest Editors:

Please address all other correspondence regarding this Special Issue to the Guest Editors using the following email-ID: nano-sm-si@listserv.unt.edu or NANO-SM-SI@unt.edu

Guest Editors

Saraju P. Mohanty, Professor, Computer Science and Engineering, University of North Texas
email: saraju.mohanty@unt.edu

Xin Li, Associate Professor, Electrical and Computer Engineering, Carnegie Mellon University,
email: xinli@cmu.edu

Hai (Helen) Li, Associate Professor, Electrical and Computer Engineering, University of Pittsburgh,
email: HAL66@pitt.edu

Yao (Kevin) Cao, Professor Electrical, Computer and Energy Engineering, Arizona State University,
email:yu.cao@asu.edu

See Call for Papers here.

TNANO Article in focus: December 2015

Wednesday, December 2nd, 2015

From the November 2015 issue of IEEE Transactions on Nanotechnology

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

by Yuhao Wang; Hao Yu ; Leibin Ni ; Guang-Bin Huang ; Mei Yan ; Chuliang Weng ; Wei Yang ; Junfeng Zhao T-NANO, Vol. 14, Issue 6, pp. 998 – 1012, November 2015.

 

7128727-fig-1-large

 

Abstract: The data-oriented applications have introduced increased demands on memory capacity and bandwidth, which raises the need to rethink the architecture of the current computing platforms. The logic-in-memory architecture is highly promising as future logic-memory integration paradigm for high throughput data-driven applications. From memory technology aspect, as one recently introduced nonvolatile memory device, domain-wall nanowire (or race-track) not only shows potential as future power efficient memory, but also computing capacity by its unique physics of spintronics. This paper explores a novel distributed in-memory computing architecture where most logic functions are executed within the memory, which significantly alleviates the bandwidth congestion issue and improves the energy efficiency. The proposed distributed in-memory computing architecture is purely built by domain-wall nanowire, i.e., both memory and logic are implemented by domain-wall nanowire devices. As a case study, neural network-based image resolution enhancement algorithm, called DW-NN, is examined within the proposed architecture. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by nonvolatile domain-wall nanowire. Domain-wall nanowire-based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that the domain-wall memory can reduce 92% leakage power and 16% dynamic power compared to main memory implemented by DRAM; and domain-wall logic can reduce 31% both dynamic and 65% leakage power under the similar performance compared to CMOS transistor-based logic. And system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 56x when compared to conventional image processing system.