IEEE Transactions on Nanotechnology
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Archive for February, 2016

TNANO & TETC Joint Special Section

Sunday, February 21st, 2016

Joint Special Section on VLSI and Nanotechnology Design Trends for Computing Innovations

IEEE Transactions on Nanotechnology and IEEE Transactions on Emerging Topics in Computing seek original manuscripts for a Special Section tentatively scheduled to appear in the September 2017 issues. The topics of interest for this special section include:

  • VLSI Design: Design of ASICs, microprocessors/micro-architectures, embedded processors, digital systems, NoC, interconnects, memories, and FPGAs.
  • VLSI Circuits: digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
  • Low Power and Power Aware Design: Circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools.
  • Computer-Aided Design (CAD): Hardware /software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floor planning, compaction), algorithms and complexity.
  • Testing, Reliability, Fault-Tolerance: Digital testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design.
  • Emerging Technologies & Post-CMOS VLSI: Analysis, circuits and architectures, modeling, CAD tools and design methodologies for nanotechnologies, molecular electronics, quantum devices, biologically-inspired computing, spintronic technology, CNT, MTJ, NML, PCM, PMC, and sensor and sensor networks, etc.

Submission Information:

Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. An extended version of an article appearing in a conference proceedings (and in particular, GLSVLSI 2016) can be submitted provided that it has substantially new content w.r.t. to the original conference version. The conference paper must be cited in the main text and the cover letter must clearly describe the differences with the conference version and clearly identify the new contributions. As an author, you are responsible for understanding and adhering to the submission guidelines. Authors are invited to submit manuscripts focused on topics of computing directly to Transactions on Emerging Topics in Computing (TETC) at https://mc.manuscriptcentral.com/tetc-cs and papers focused on topics of nanoscale circuits and technology directly to Transactions on Nanotechnology (TNano) at https://mc.manuscriptcentral.com/tnano. Authors should be aware that papers can be published in TNano or TETC depending on the availability of space with the final allocation at the discretion of the Editor-in-Chief of the respective Transactions. Please address all correspondence regarding this Special Section to the Guest Editors (email: tpc.chairs@gmail.com).

Important Dates:

The following is the tentative timeline for the special issue:

  • Submission Deadline: September 30, 2016
  • Author Notification: December 1, 2016
  • Revised Manuscript Due: February 1, 2017
  • Notification of Acceptance: May 1, 2017
  • Final Manuscript Due: June 1, 2017
  • Tentative Publication Date: September 2017

Guest Editors

Laleh Behjat, University of Calgary,

Ayse Coskun, Boston University

Jie Han, University of Alberta

Martin Margala, University of Massachusetts Lowell

See Call for Papers here.

TNANO Article in focus: February 2016

Saturday, February 6th, 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Computationally Efficient Multiple-Independent-Gate Device Model

by A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli,
T-NANO, Vol. 15, Issue 1, pp. 2 – 14, January 2016.

 

feb2016

Abstract: Nanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.