IEEE Transactions on Nanotechnology
IEEE

Archive for September, 2016

TNANO Article in focus: September 2016

Thursday, September 8th, 2016

From the September 2016 issue of IEEE Transactions on Nanotechnology

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

by YYasunao Katayama; Toshiyuki Yamane; Daiju Nakano; Ryosho Nakane; Gouhei Tanaka
T-NANO, Vol. 15, Issue 5, pp. 762 – 769, September 2016.

 
Immagine

Abstract: We present a framework of wave-based neuromorphic computing aiming at brain-like capabilities and efficiencies with nanoscale device integration. We take advantage of the unique nature of elastic nondissipative wave dynamics in both computations and IO communications in between as a means to natively implement and execute neuromorphic computing functions such as weighted sum in a spatiotemporal manner. Lower bound analysis based on a memory model and wave group velocity scaling is provided for conceptual evaluations.
 

TNANO Article in focus: August 2016

Thursday, September 8th, 2016

From the July 2016 issue of IEEE Transactions on Nanotechnology

Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic-Based Reconfigurable Architecture

by Kamela C. Rahman; Dan Hammerstrom; Yiwei Li; Hongyan Castagnaro; Marek A. Perkowski
T-NANO, Vol. 15, Issue 4, pp. 675 – 686, July 2016.

 
teaser0816

Abstract: Continued dimensional scaling of CMOS processes is approaching fundamental limits and, therefore, alternate new devices and microarchitectures are explored to address the growing need of area scaling and performance gain. New nanotechnologies, such as memristors, emerge. Memristors can be used to perform stateful logic with nanowire crossbars, which allows for implementation of very large binary networks. This paper involves the design of a memristor-based massively parallel datapath for various applications, specifically single instruction multiple data and parallel pipelines. The innovation of our approach is that the datapath design is based on space-time diagrams that use stateful IMPLY gates built from binary memristors. The paper also develops a new model and methodology to design massively parallel memristor-CMOS hybrid datapath architectures at a system level. This methodology is based on an innovative concept of two interacting subsystems: 1) a controller composed of a memristive RAM, MsRAM, to act as a pulse generator, along with a finite-state machine realized in CMOS, a CMOS counter, CMOS multiplexers, and CMOS decoders; 2) massively parallel pipelined datapath realized with a new variant of a CMOL-like nanowire crossbar array, memristive stateful CMOL with binary stateful memristor-based IMPLY gates. In contrast to previous memristor-based FPGA, our proposed memristive stateful logic field programmable gate array uses memristors for both memory and combinational logic implementation. With a regular structure of square abutting blocks of memristive nanowire crossbars and their short connections, our architecture is highly reconfigurable. We present the design of a pipelined Euclidean distance processor along with its various applications. Euclidean distance calculation is widely used by many neural network and similar algorithms.