IEEE Winnipeg Section


EduManCom Seminar



Designing High Speed External Memory Interfaces in Altera FPGAs


Monday, October 3, 2011 @ 4:00-5:00pm


E3-270, EITC Building, University of Manitoba Fort Garry Campus


Kalen Brunham, P.Eng
Senior Member of the Technical Staff
Altera Corporation
Toronto, Ontario


The fundamental challenge in designing high speed external memory interfaces for protocols such as DDR3 is the unknown phase relationship between the memory components and the memory controller. In addition, static timing analysis breaks down as it does not take into account the reduction in pessimism as a result of memory interface calibration. This presentation outlines these challenges and reviews how Altera addresses them by building self calibrating memory controllers and employing cutting edge flexible static timing analysis.

Speaker Bio:

Kalen Brunham is a Senior Member of the Technical Staff in the Software and IP department at Altera’s Toronto Technology Center. Over the 8 years he has been with Altera he has been involved in a number of projects including competitive architecture analysis, external memory interface IP development, and IP usability. His current interests are in debug tools for external memory interfaces and high level IP integration in FPGAs. Kalen holds an M.Sc from the University of Manitoba in the area of signal and data compression.


IEEE EduManCom Chapter & Department of Electrical & Computer Engineering.


This will be a free event.


For questions or more information: Ken Ferens 474-8517

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