IEEE Winnipeg Section


UofM ECE Department Seminar



Timing Analysis for Digital Systems


Friday, March 15, 2013 at 1:30pm


E2-320 EITC Building, University of Manitoba Fort Garry Campus


Dr. Reza Azarderakhsh
University of Waterloo


Digital systems are usually targeted to operate at specific clock frequencies. This property becomes important when we deal with small and embedded digital systems. Gauging the ability of a circuit to operate at the specified speed requires measuring its delay at numerous steps during the design process. This lecture discusses the basic structure of synchronized clocked designs and how they behave on a clock cycle to clock cycle basis. We first discuss FPGA and ASIC design flows and illustrate the importance of timing analysis. We describe static timing analysis and dynamic timing analysis and discuss their properties. In the case of static timing analysis, we then go into properties of the clock and derive the logic delay constraints for flipflop based designs.

We illustrate set up and hold time and derive timing equations for flip-flop based designs. We present timing parameters including critical-path delay, latency, throughput and provide relevant examples. We also talk about false paths and multi-cycle paths and why they need to be excluded from the timing calculations. Finally, we describe the concepts of clock domains and crossing the clock domains for systems operating with more than one clock frequency. This lecture is in part based on RTL Hardware Design Using VHDL, by P. P. Chu and Digital System Design Using VHDL, by Ch. H. Roth and L. K. John.


This will be a free event.


For questions or more information: Lorraine Coates at 474-9099

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