IEEE Winnipeg Section

IEEE

IEEE Computer and Computational Intelligence Seminar – High Level Design Tools for FPGAs (Jan. 4, 2018)

The Department of Electrical and Computer Engineering and the IEEE Winnipeg Section Computer and Computational Intelligence Chapter is pleased to present:

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Seminar Title: High Level Design Tools for FPGAs

Speaker: Paul White

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Date: Thursday January 4, 2018 – 2:30 PM to 3:30 PM

Location: EITC E2-350, University of Manitoba, 75 Chancellor’s Circle, Winnipeg, MB, Canada

Contact: Ian Jeffrey, Chair, IEEE Computer and Computational Intelligence Chapter, Winnipeg – Ian.Jeffrey@umanitoba.ca

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Presentation Abstract:

High-level languages are commonplace in software design, and now they are coming to FPGAs too! In this talk, you will learn about some of Intel PSG’s High Level Design tools for FPGAs. These tools include the brand new High Level Synthesis (HLS) compiler, as well as DSP Builder, and OpenCL.

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Biography of the Speaker:

Paul White graduated from the University of Manitoba Dept. of Computer Engineering in 2014, and completed a MSc. in Biomedical Engineering in 2017. He currently works at Intel Programmable Solutions Group as an Application Engineer supporting the newly released Intel HLS compiler.

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